﻿ 一种基于FPGA的新型全数字锁相环的建模与分析

# 一种基于FPGA的新型全数字锁相环的建模与分析Modeling and Analysis of a Novel All-Digital Phase-Locked Loop Based on FPGA

Abstract: This paper proposed a novel all-digital phase-locked loop (ADPLL). By using the self-sampling PI control method, it can obtain a phase-locked output signal without steady-state error and with less jitter. The designed ADPLL is able to adjust the mode number of the digital loop filter according to the phase error between the two input signals of the digital phase detector. In this way, the ADPLL can optimize the lock-in speed when the system stability is also guaranteed. The paper establishes the mathematical model of the ADPLL based on the analysis of the operating characteristic of each module. Using the obtained system transfer function, the paper analyzes the performance parameters of the ADPLL, and provides the guiding principle of the parameters design. The validity of theoretical analysis is verified by experimental test in the final of this paper.

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