Dynamic Voltage Assignment Technique for Cell Based Design under Power and Performance Constraints
作者: 郑经华 ：逢甲大学电子工程学系，台中;
Abstract: Lowering on selected blocks helps to reduce power significantly. Unfortunately, lowering the voltage also increases the delay of the gates in the design. Multi-voltage design is an effective way to reduce power consump- tion. High voltage is applied to the critical function or path, while low voltage is applied to non-critical paths. If the designer wants to choose different performance levels in the same design, designer needs to know how to program the voltage of the cell. This method reduces power consumption and not only maintains the same circuit performance but also saves power. In the proposed methodology of this paper, supply voltage applied to logic gates is programmable, and logic gates can be specified to high or low voltage domains according to operating system requirements. In order not to violate the delay time, the logic gates on the critical path require higher voltage. Lower voltage on the logic gates can be assigned to partial non-critical paths simultaneously. In the proposed method, the power switches possess the feature of flexible programming. They can easily be controlled according to the user requirement after chip manufacture. The potential of this design is that voltage domain can be switched to either high or low based on different design con- straints, e.g. voltage drop and temperature increase. The characteristic of this mechanism is programmable re-design of voltage domain after chip fabrication. The chip function proof this novel methodology is fully successful used in power-performance tradeoff application.
文章引用: 郑经华 (2013) 具效能和功率考虑之动态电压规划技术与自动化流程设计之实现。 电路与系统， 2， 30-37. doi: 10.12677/OJCS.2013.22006
 T. D. Burd, T. A. Pering, A. J. Stratakos and R. W. Brodersen. A dy-namic voltage scaled microprocessor system. IEEE Journal of Solid-State Circuits, 2002, 35(11):1571-1580.
 R. Blanco, J. M. Cohn, D. W. Stout and S. T. Ventrone. Method of switching voltage islands in integrated circuits. Patent Appli- cation Publication, US 2006/0190744 A1.
 R. Puri, D. Kung and L. Stok. Minimizing power with flexible voltage islands. IEEE International Symposium on Circuits and Systems, 23-26 May 2005, 1: 21-24.
 B. H. Calhoun, A. P. Chandrakasan. Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering. IEEE Journal of Solid-State Circuits, 2006, 41(1): 238-245.
 J. Luo, N. Jha. Static and dynamic variable voltage scheduling algorithmus for real-time heterogeneous distributed embedded systems. IEEE Proceedings of the 15th International Conference on VLSI Design, Bangalore, 2002: 719-726.
 K. Usami, et al. Clustered voltage scaling technique for low- power design. Proceedings of the 1995 International Symposium on Low Power Design (ISLPD’95), Dana Point, 23-26 April 1995: 3-8.
 K. Usami, et al. Automated low power technique exploiting mul- tiple supply voltages Applied to a Media Processor. Proceedings of the Custom Integrated Circuits Conference, Santa Clara, 5-8 May 1997: 131-134.
 T. S. Jau. Single-inductor multiple-output DC-DC converters for STV-CMOS. Master’s Thesis, 中正大学, 2004.
 S. H. Kulkarni, D. Sylvester. High performance level conversion for dual VDD design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2004, 12(9): 926-936.
 S. A. Tawfik, V. Kursun. Multi-Vth level conversion circuits for Multi-VDD systems. IEEE International Symposium on Circuits and Systems, New Orleans, 27-30 May 2007: 1397-1400.
 J.-W. Lin, C.-W. Dr. Yeh. Clus-ter-inclined supply and threshold voltage scaling with gate re-sizing. Master’s Thesis, 中正大学, 1994.
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