CSA

编委详情

基本情况

董社勤,清华大学计算机系副教授。

 

研究领域

计算机软件与理论(集成电路物理设计理论与方法,现代智能优化算法,基于多核片上系统的大数据高性能计算,片上系统设计理论与方法,片上网络设计理论与方法,多核系统设计理论与方法)


论文发表

  1. Dong, Sheqin, Ao, Jianchang), Luo, Fuqi), Delay-Driven and Antenna-Aware Layer Assignment in Global Routing Under Multitier Interconnect Structure, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 34, No.5, pp740-752, 2015
  2. Kan Wang, Sheqin Dong, Huaxi Wang,Qian Chen, Tao Lin, Mixed-crossing-avoided Escape Routing of Mixed-Pattern Signals on Staggered-Pin-Array PCBs",IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. Vol. 33, No.4, pp571-584, 2014
  3. Ou He, Sheqin Dong, Wooyoung Jang, Jinian Bian, David Z. Pan: UNISM: Unified Scheduling and Mapping for General Networks on Chip. IEEE Transaction on VLSI Syst.20(8): 1496-1509 (2012)
  4. Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong: Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. IEICE Transactions94-A(12): 2490-2498 (2011)
  5. Wenxu Sheng, Sheqin Dong: Multi-bend bus-driven floorplanning considering fixed-outline constraints.Integration 46(2): 142-152 (2013)
  6. Haiqi Wang, Sheqin Dong, Tao Lin, Song Chen, Satoshi Goto: Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System.IEICE Transactions 95-A(12): 2208-2219 (2012)
  7. Xu He, Sheqin Dong, Yuchun Ma: Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. Integration 43(4): 342-352 (2010)
  8. Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto: Voltage and Level-Shifter Assignment Driven Floorplanning.IEICE Transactions 92-A(12): 2990-2997 (2009)
  9. Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto: Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis.IEICE Transactions 92-A(9): 2283-2294 (2009)
  10. Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto: Cluster Generation and Network Component Insertion for Topology Synthesis ofApplication-Specific Network-on-Chips. IEICE Transactions 95-C(4): 534-545 (2012)
  11. Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto, “Fast Custom Instruction Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design”, IEICE Trans. Fundamentals, Vol. E91-A, No.6, pp. 1478-1487, June 2008
  12. Chen, S (Chen, Song)(&); Dong, SQ (Dong, Sheqin)(*); Hong, XL (Hong, Xianlong); Ma, YC (Ma, Yuchun); Cheng, CK (Cheng, C. K.), VLSI block placement with alignment constraints, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol.53, pp622-626, 2006
  13. Hong, XL (Hong, XL); Dong, SQ (Dong, SQ)(*); Huang, G (Huang, G); Cai, YC (Cai, YC); Cheng, CK (Cheng, CK); Gu, J (Gu, J)Corner block list representation and its application to floorplan optimization,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol.51, pp228-233, 2004
  14. Ma, YC (Ma, YC)(&); Hong, XL (Hong, XL); Dong, SQ (Dong, SQ)(*);Chen, S (Chen, S); Cheng, CK (Cheng, CK); Gu, J (Gu, J)Buffer planning as an integral part of floorplanning with consideration of routing congestion, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 24, pp609-621, 2005
  15. Ma, YC (Ma, YC)(&); Hong, XL (Hong, XL); Dong, SQ (Dong, SQ)(*); Cai, YC (Cai, YC); Cheng, CK (Cheng, CK); Gu, J (Gu, J)Stairway compaction using corner block list and its applications with rectilinear blocks, ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, Vol.9, pp199-211, 2004
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